----------------------------------------------------------------------------------
-- Company:        RIT
-- Engineer:       Sam Skalicky
-- 
-- Create Date:    17:49:05 12/11/2009 
-- Design Name:    MSD P10662
-- Module Name:    Device - Behavioral 
-- Project Name:   Inout
-- Target Devices: Spartan 6 LXT
-- Tool versions:  QuestaSim-64 6.4c
-- Description:    This a bi-directional I2C/Two-wire port implementation in VHDL
--
-- Notes: Data is the bi-directional port, Clk is typeset as an inout in the idea that
-- the clock could be generated to this port (Master device) or recieved from this port
-- in the case of a Slave device. However it is not meant to be a bi-directional port
--
-- Dependencies:   None
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity I2Cmaster is
    Generic (register_data_width : natural;
             register_id_width : natural);
    Port ( PS2_Clk : in  STD_LOGIC;
           FPGAClk : in std_logic;
			  I2C_Clk_out : out std_logic;
           Send : in std_logic;
           Instruction : in std_logic_vector(7 downto 0);
           register_id : in std_logic_vector(register_id_width-1 downto 0);
           Data : in std_logic_vector(register_data_width-1 downto 0);
			  I2C_Dir : out std_logic;
			  I2C_InFromBus : in std_logic;
			  I2C_OutToBus : out std_logic);
end I2Cmaster;
